Thus far, a technology that performs signal output simultaneously from a plurality of pixels belonging to the same pixel column has been known (for example, see Patent Literature 1).
Patent Literature 1 discloses a solid-state imaging element of a configuration in which a plurality of vertical signal lines are provided to correspond to pixel columns of a pixel array section, two column circuits (signal processing circuits) each of which performs prescribed signal processing on pixel signals outputted through the corresponding one of the plurality of vertical signal lines are arranged for each pixel column, and high-sensitivity signals and low-sensitivity signals outputted from one pixel through vertical signal lines are processed in parallel by the two column circuits. A signal outputted from each pixel of a selected row is supplied to one of the two column circuits through the corresponding one of the vertical signal lines.
The scanning of the pixel array section is performed on a pixel row basis. Types of scanning include electronic shutter scanning for removing charge accumulated in a photoelectric conversion element of a pixel and readout scanning for reading out charge accumulated in the photoelectric conversion element. In the technology described in Patent Literature 1, readout scanning is performed twice.
In a case where the time required to perform scanning from a pixel row on which electronic shutter scanning is performed (hereinafter, a “shutter row”) to a pixel row on which the first round of readout scanning is performed (hereinafter, “readout row 1”) is referred to as accumulation time 1 and the time required to perform scanning from readout row 1 to a pixel row on which the second round of readout scanning is performed (hereinafter, “readout row 2”) is referred to as accumulation time 2, two signals with different sensitivities, that is, a low-sensitivity signal and a high-sensitivity signal can be obtained by making accumulation times 1 and 2 different.